The invention relates to an arrangement for correcting burst errors with a maximum length of b bits according to the "Error Trapping" method in cyclical block codes shortened by i bits and having n bits composed of r bits for a check part and of k bits for an information part. A syndrome register having r stages is provided whereby an input is connected via at least one exclusive-OR gate connected between these stages. The position of the exclusive-OR gate is derived from the coefficients of a pre-multiplication polynomial. The output of the last stage is connected via a first switch to the input of the first stage and via at least one further exclusive-OR gate connected between the stages to further stages. The position thereof is derived from the generator polynomial of the code. A zero recognition means having r-b stages and connected to the stages of the syndrome register and a buffer memory having n stages and connected to the overall input is provided. A last exclusive-OR gate whose one input is connected to the output of the buffer memory, whose other input is connected via a second switch to the output of the syndrome register, and whose output is connected to the overall output is provided. An executive sequencer actuates all switches synchronously with a synchronization signal at the overall input. A clock supply is provided synchronized with the bit clock of the reception signal present at the overall input.
Such an arrangement is known from the book by W. Wesley Peterson, E. J. Weldon, Jr., Error Correcting Codes, The MIT Press, Cambridge, Mass., 1972, pages 364-370, especially FIG. 11.4, incorporated herein by reference.
In cyclical block codes, particularly for the correction of burst errors having the length b, the so-called "Error Trapping" method is a standard correction procedure. A cyclical block code is defined by its generator polynomial g(x).
At the transmit side, a check part is connected to the information part by means of a syndrome register having r stages. A code word thus arises that can be mathematically represented as a polynomial with binary coefficients. This code word can be falsified in the transmission. It is referenced v(x) at the receive side.
A receive-side decoding likewise occurs by means of a syndrome register having r stages. After input of the received code word, this contains nothing but zeros given freedom from error. When, by contrast, errors are present, ones also appear. The bit pattern in the syndrome register after input of the code word is referred to as syndrome.
In order to be able to begin immediately with the error correction after the decoding, an automatic pre-multiplication of the n-bit receive word v(x) to be interpreted as polynomial is undertaken by the polynomial x.sup.r. In terms of circuit technology, this means that the receive word after the last stage of the syndrome register is input via an exclusive-OR gate. The error correction begins after the conclusion of the input. For this purpose, the content of the syndrome register is cyclically shifted given a closed feedback until the first r-b stages contain only zeros. The last b stages then contain the error pattern.
When the block code is to be shortend by i bits, then the first i bits of the information code of every code word are set to zero and omitted after the coding. In the decoding, the shortened code word must be filled with zeros again. The attachment of zeros can be avoided when an additional pre-multiplication of the received code word is undertaken with the polynomial x.sup.i, i.e. given a shortened block code the syndrome of the polynomial of the received code word v(x) multiplied by the polynomial p.sub.1 (x) is calculated. For the realization of this pre-multiplication, the pre-multiplication polynomial p.sub.1 (x) must first be calculated, this deriving as a division remainder in the division of the polynomial x.sup.r+i by the generator polynomial g(x): EQU p.sub.1 (x)=rem{i.sup.r+i :g(x)}
The coefficients of p.sub.1 (x) define the places at which the receive word must be input into the syndrome register via exclusive-OR gates.
In the known correction arrangement for the shortened block code, a plurality of additional exclusive-OR gates are generally required in comparison to the correction arrangement for the unshortened code, even given a shortening by only a few bits.